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multi-power supply rv5ve0 series application manual no.ea-021-0006
multi-power supply 1 rv5ve0 series outline the rv5ve0 series are multi-power supply ics with high accuracy output voltage and detector threshold and with ultra low supply current by cmos process. each of these ics consists of four voltage regulators,two volt- age detectors and control switches.these ics can achieve the construction of an ideal power supply system in accordance with the user's mask option. output voltage and detector threshold can be independently set within each ic by laser trim. the package are of 16pin ssop(0.8mm pitch) and 16pin ssop(0.65mm pitch). ? ultra-low supply current ? broad operating voltage range ..................... 1.5v to 10.0v ? high accuracy output voltage and detector threshold ..................................................... 2.5% ? output voltage and detector threshold ........ stepwise setting with a step of 0.1v is possible (refer to selection guide) ? low temperature-drift coefficients of output voltage and detector threshold ............. typ. 100ppm/?c ? small dropout voltage ..................................... 50mv when i out is 80ma (regulators 1, 2) ? small package .................................................. 16pin ssop (0.8mm pitch) 16pin ssop (0.65mm pitch) ? direct connection to cpu is possible by an internal level shift circuit. features applications ? power source system for hand-held communication equipment such as cellular phones and cordless telephones. ? power source system for battery-powered appliances. pin configuration ? rv5ve001 v sen2 c d reset d out i bc1 gnd v dd csw3 r out2 i bc2 r out1 2 v sen1 csw2 csw1 r out4 1 3 4 6 8 5 7 9 10 11 16 15 13 14 12 r out3
2 part number is designated as follows : rv5ve0 C ? part number ----- abcde selection guide in the rv5ve0 series, standard ics and customized ics by mask option (hereinafter optional mask version ics) are available at the user's request. voltage settings for six circuits, four for regulators and two for detectors, can be designated. } code contents a designation of package type: v : 16pin ssop (0.65mm pitch) b serial number for multi-power supply ic (rv5ve) series: serial number for mask version: c 1 for standard ics. other numbers for optional mask version ics. d serial number for voltage setting: a to z are assigned in alphabetical order. (except i,o,q,x) designation of taping type: e ex. e1, e2 (refer to taping specifications) rv5ve0 block diagrams csw1 v sen1 reset c d gnd v sen2 level shift r out1 i bc1 regulator 2 csw2 csw3 i bc2 r out2 r out3 r out4 d out level shift level shift regulator 1 regulator 3 detector 2 detector 1 delay generator v dd regulator 4 ? rv5ve001 v dd detector 2 c d gnd d out regulator 1 r out1 i bc1 reset r out2 i bc2 r out3 r out4 regulator 2 regulator 3 regulator 4 detector 1 delay generator t q q r one shot pulse generator to be named by uesr ? rv5ve0 (optional mask version) }
3 pin description pin no. symbol 1r out 4 2v sen 2 3c d 4 reset 5d out 6r out 1 7i bc 1 8 gnd 9i bc 2 10 r out 2 11 csw1 12 csw2 13 csw3 14 v sen 1 15 r out 3 16 v dd description output pin for voltage regulator 4. sense pin for voltage detector 2. pin for external capacitor for delay time setting of voltage detector 2. output pin of voltage detector 2. nch open drain output. l outputat detection. output pin of voltage detector 1. nch open drain output. l output at detection. output pin of voltage regulator 1. connected to collector of pnp transistor. connected to base of external pnp transistor for voltage regulator 1 and controls base current. ground pin. connected to base of external pnp transistor for voltage regulator 2 and controls base current. output pin of voltage regulator 2. connected to collector of pnp transistor. control switch input pin for turning voltage regulator 1 on/off. input level for this input pin is active h . control switch input pin for turning voltage regulator 2 on/off. input level for this input pin is active h control switch input pin for turning voltage regulator 3 on/off. input level for this input pin is active h . sense pin of voltage detector 1. output pin of voltage regulator 3. v dd pin. ? rv5ve001 (standard ics) ? rv5ve0 (optional mask version ics) pin no. symbol 2 11 12 13 14 description 5 pins nos. 2, 11, 12, 13 and 14 can be designated as input pins by user's choice. refer to optional mask version guide. pins other than the above 5 pins can be selected from the same pins as those used in r 5ve001 (standard ics) to be named by user rv5ve0
4 optional mask version guide user can designate an optional mask version in accordance with the following optional mask version guide: ? functions of input pins by user' choice pin no. symbol 2 11 12 13 14 functions control switch of each circuit, sense pin of voltage detector 1 or 2. control switch of each circuit, schmitt trigger input possible. control switch of each circuit only. control switch of each circuit only. control switch of each circuit, sense pin of voltage detector 1 or 2. to be named by user item sense pins of voltage detectors 1, 2 on/off control of regulators and detectors on/off control by toggle input (only pin 11) pins by user's choice output of voltage detectors 1, 2 description ? sense pins of voltage detectors 1, 2 can be connected to output r out 1 , r out 2 , r out 3 , r out 4 of voltage regulators, or v dd . ? on/off control of voltage regulators 1 to 4 and voltage detector 1 can be per- formed by 3 input and gate. ? on/off control of voltage detector 2 can be directly performed. ? on/off control of 4 voltage regulators and 2 voltage detectors can be per- formed by and gate of toggle input and level input. ? edge trigger flip-flop (rise edge operation) is reset and initialized at the rise of power source or at the detection operation of voltage detector 1 or 2. ? flip-flop can be reset by one shot pulse at the detection of voltage detector 1 or 2, or the reset state can be maintained during the detection operation. ? five input pins are available as user's pins as shown in the table shown below. ? on/off control input pins for regulators and detectors. ? sense pins of voltage detectors 1,2. ? active h input or active l input can be selected. ? reset output and d out output, which are output from voltage detectors 1, 2, can be set at l or h at the time of the detection. ? reset output and d out output, which are output from voltage detectors 1, 2,can be set at l or h at the time of off by on/off control. ? output signals of voltage detectors 1, 2 can perform on/off control of voltage regulators 1 to 4. rv5ve0
5 rv5ve0 description of each circuit 1. voltage regulators 1,2 ? voltage regulators 1, 2 are linear regulators which can be constructed of external pnp transistor, and are capa- ble of obtaining a large output current by a small dropout voltage. ? output voltage of each of voltage regulators 1, 2 can be set stepwise with a step of 0.1v in the range of 3v to 6v by laser trim. ? voltage regulators 1, 2 can be turned on/off by control pins. ? use external pnp transistor of a low saturation type, with an h fe of 100 or more. ? use voltage regulators 1, 2 with the attachment of a capacitor with a capacitance of 10f or more to the output pins. 2. voltage regulators 3,4 ? voltage regulators 3, 4 are cmos type linear regulators and have the same structure as those of voltage regulators r 5rl and r 5re series. ? output voltage of each of voltage regulators 3, 4 can be set stepwise with a step of 0.1v in the range of 2v to 6v by laser trim. ? voltage regulators 3, 4 can be turned on/off by control pins. 3. voltage detector 1 ? when voltage detector 1 detects the lowering of v sen 1 , the level of the output of voltage detector 1 becomes l level. the output of voltage detector 1 is nch open drain output. ? voltage detector 1 can be set as follows by optional mask: 1. on/off control of voltage detector 1. 2. output of voltage detector 1 at the detection can be set at l level or h level. 3. output of voltage detector 1 at off can be set at l level or h level. 4. sense pins of voltage detectors 1, 2 can be connected to output r out 1 , r out 2 , r out 3 , r out 4 of voltage regulators or v dd within the ic. 4. voltage detector 2 ? when voltage detector 2 detects the lowering of v sen 2 , the level of the output of voltage detector 2 becomes l level. the output of voltage detector 2 is nch open drain output. ? voltage detector 2 can set reset delay time. delay time can be set in accordance with the capacitance c d of external capacitor as shown on the following pages. ? voltage detector 2 can be set as follows by optional mask: 1. on/off control of voltage detector 2. 2. output of voltage detector 2 at the detection can be set at l level or h level. 3. output of voltage detector 2 at off can be set at l level or h level. 4. sense pins of voltage detectors 2 can be connected to output r out 1 , r out 2 , r out 3 , r out 4 of voltage regulators or v dd within the ic.
6 current source extermal capacitor r d gnd v dd reset v sen2 c d v ref + 5. main power source control (in the case of optional mask version) ? this ic includes built-in edge trigger flip-flop (rising edge operation) and and gate, so that main power source of any instruments can be turned on/off by and of toggle input and level input. ? edge trigger flip-flop is reset by one shot pulse generator when voltage detector 1 or 2 detects the lowering of the voltage. this flip-flop can be continuously reset during the detection. rv5ve0 ? formula for calculating reset delay time is t d = 0.69 r d c d wherein r d is the resistance of a built-in resistor and can be set at 1m in ic, so that the above formula is: t d = 0.69 10 6 c d voltage detector with delay circuit is constructed as shown below. ? block diagram of voltage detector with delay circuit.
7 ? electrical characteristics of r 5ve001 symbol item v in input voltage v out output voltage i out output current p d 1 power dissipation1 (16pin ssop (0.8mm pitch)) p d 2 power dissipation2 (16pin ssop (0.65mm pitch)) topt operating temperature range tstg storage temperature range tsolder lead temperature(soldering) rating unit +12 v C0.3 to v in +0.3 v 300 ma 500 mw 470 mw C 30 to +80 ?c C 40 to +125 ?c 260?c 10s absolute maximum ratings overall characteristics symbol item v dd operationg voltage range r out 1 , 2 output voltage setting range 1 r out 3 , 4 output voltage setting range 2 Cv det detector threshold setting range conditions min. typ. max. unit 1.5 10.0 v step of 0.1v 3.0 6.0 v step of 0.1v 2.0 6.0 v step of 0.1v 2.0 6.0 v the following three types of ics are available as standard ics.the details of these ics are shown in the section of electrical characteristics on the following pages: ? list of standard voltage settings type number r 5ve001a r 5ve001b r 5ve001c output voltage of regulator 1 to 4 5.0v 4.0v 3.0v threshold voltage of detector 1 5.4v 4.4v 3.4v threshold voltage of detector 2 4.5v 3.5v 2.5v conditions for input voltage 6.0v 4.8v 3.6v rv5ve0 absolute maximum ratings are threshold limit values that must not be exceeded even for an instant under any conditions. moreover, such values for any two items must not be reached simultaneously. operation above these absolute maximum ratings may cause degradation or permanent damage to the device. these are stress ratings only and do not necessarily imply functional operation below these limits. absolute maximum ratings
8 ? rv5ve001a (note 1) unless otherwise provided, v dd = 6.0v, i out = 50ma, co = 10f, rbe = 100k . (note 2) use external transistor with h fe 3 100. (note 3) quiescent current = operating current of regulators 1, 2 + 0.6/rbe. (note 4) supply current = quiescent (no load) current + load current/h fe . symbol item r out 1 , 2 output voltage i ss 1 , 2 quiescent current iopr 1 , 2 supply current v dif 1 , 2 dropout voltage ? v out load regulation ? i out ? v out line regulation ? v in rr ripple rejection i lim1,2 current limit ? v out output voltage ? topt temperature coefficient conditions min. typ. max. unit 4.875 5.000 5.125 v i out =0ma 100 a i out =80ma 1 ma r out 1 , 2 =5.0v,i out =80ma 0.05 0.3 v r out 1 , 2 =5.0v 1ma i out 80ma 50 mv r out 1 , 2 +0.3v v in 10.0v 0.05 0.3 %/v f=120h z ,ripple 0.5vrms 40 60 db base current of i b 1 , 2 of 310ma pnp transistor 100 ppm/?c topt=25?c voltage regulator 3 [rv5ve001a] symbol item r out 3 output voltage i ss 3 supply current v dif 3 dropout voltage ? v out load regulation ? i out ? v out line regulation ? v in i lim3 current limit ? v out output voltage ? topt temperature coefficient conditions min. typ. max. unit 4.875 5.000 5.125 v 5.0 10.0 a r out 3 =5.0v,i out =50ma 0.3 v r out 3 =5.0v 1ma i out 50ma 50 mv r out 3 +0.5v v in 10.0v 0.05 0.3 %/v 100 300 ma 100 ppm/?c topt=25?c voltage regulators 1, 2 [ rv5ve001a] (note) unless otherwise provided, v dd = 6.0v, i out = 30ma rv5ve0
9 rv5ve0 voltage regulator 4 [rv5ve001a] topt=25?c (note) unless otherwise provided, v dd = 6.0v, i out = 10ma voltage detectors 1,2 [rv5ve001a] symbol item Cv det 1 detector threshold 1 Cv det 2 detector threshold 2 v hys detector threshold hysteresis i ss 5 i ss 6 supply current i out output current r d output delay resistor i sen sense pin input current ? v det detector threshold ? topt temperature coefficient conditions min. typ. max. unit voltage detector 1 5.265 5.400 5.535 v voltage detector 2 4.388 4.500 4.612 v ( C v det ) 0.05 v voltage detector 1,v dd =6.0v 1.3 3.9 a voltage detector 2,v dd =6.0v 1.5 4.5 a v ds =0.5v, v dd =1.5v 1.5 ma v ds =0.5v, v dd =6.0v 11.6 voltage detector 2 only 0.5 1.0 2.0 m v sen =6.0v 0.5 2 a 100 ppm/?c topt=25?c (note) unless otherwise provided, v dd = 6.0v. symbol item r out 4 output voltage i ss 4 supply current v dif 4 dropout voltage ? v out load regulation ? i out ? v out line regulation ? v in i lim4 current limit ? v out output voltage ? topt temperature coefficient conditions min. typ. max. unit 4.875 5.000 5.125 v 1.3 3.9 a r out 4 =5.0v,i out =20ma 0.3 v r out 4 =5.0v 1ma i out 20ma 50 mv r out 4 +0.5v v in 10.0v 0.05 0.3 %/v 100 300 ma 100 ppm/?c
10 input pins [rv5ve001a] symbol item i leak input leakage current v il control switch low level input voltage v ih control switch high level input voltage v sil schmitt trigger low level input voltage v sih schmitt trigger high level input voltage v hys schmitt trigger hysteresis voltage conditions min. typ. max. unit C1 1 a csw1 to 4 0 0.8 v csw1 to 4 2.4 v dd v optional v optional v optional v topt=25?c (note) unless otherwise provided, v dd = 6.0v. rv5ve0
11 ? rv5ve001b (note 1) unless otherwise provided, v dd = 4.8v, i out = 50ma, co = 10f, rbe = 100k . (note 2) use external transistor with h fe 3 100. (note 3) quiescent current = operating current of regulators 1, 2 + 0.6/rbe. (note 4) supply current = quiescent (no load) current + load current/h fe . voltage regulator 3 [rv5ve001b] voltage regulators 1, 2 [rv5ve001b] (note) unless otherwiseprovided, v dd = 4.8v, i out = 30ma. topt=25?c topt=25?c rv5ve0 symbol item r out 1 , 2 output voltage i ss 1 , 2 quiescent current iopr 1 , 2 supply current v dif 1 , 2 dropout voltage ? v out load regulation ? i out ? v out line regulation ? v in rr ripple rejection i lim1,2 current limit ? v out output voltage ? topt temperature coefficient conditions min. typ. max. unit 3.900 4.000 4.100 v i out =0ma 100 a i out =80ma 1 ma r out 1 , 2 =4.0v,i out =80ma 0.05 0.3 v r out 1 , 2 =4.0v 1ma i out 80ma 50 mv r out 1 , 2 +0.3v v in 10.0v 0.05 0.3 %/v f=120h z ,ripple 0.5vrms 40 60 db base current of i b 1 , 2 of 310ma pnp transistor 100 ppm/?c symbol item r out 3 output voltage i ss 3 supply current v dif 3 dropout voltage ? v out load regulation ? i out ? v out line regulation ? v in i lim3 current limit ? v out output voltage ? topt temperature coefficient conditions min. typ. max. unit 3.900 4.000 4.100 v 5.0 10.0 a r out 3 =4.0v,i out =43ma 0.3 v r out 3 =4.0v 1ma i out 43ma 50 mv r out 3 +0.5v v in 10.0v 0.05 0.3 % /v 100 300 ma 100 ppm/?c
12 voltage regulator 4 [rv5ve001b] topt=25?c (note) unless otherwise provided, v dd = 4.8v, i out = 10ma voltage detectors 1,2 [rv5ve001b] topt=25?c (note) unless otherwise provided, v dd = 4.8v. rv5ve0 symbol item r out 4 output voltage i ss 4 supply current v dif 4 dropout voltage ? v out load regulation ? i out ? v out line regulation ? v in i lim4 current limit ? v out output voltage ? topt temperature coefficient conditions min. typ. max. unit 3.900 4.000 4.100 v 1.3 3.9 a r out 4 =4.0v,i out =17.5ma 0.3 v r out 4 =4.0v 1ma i out 17.5ma 50 mv r out 4 +0.5v v in 10.0v 0.05 0.3 %/v 100 300 ma 100 ppm/?c symbol item Cv det 1 detector threshold 1 Cv det 2 detector threshold 2 v hys detector threshold hysteresis i ss 5 i ss 6 supply current i out output current r d output delay resistor i sen sense pin input current ? v det detector threshold ? topt temperature coefficient conditions min. typ. max. unit voltage detector 1 4.290 4.400 4.510 v voltage detector 2 3.413 3.500 3.587 v (Cv det ) 0.05 v voltage detector 1,v dd =4.8v 1.2 3.6 a voltage detector 2,v dd =4.8v 1.4 4.2 a v ds =0.5v, v dd =1.5v 1.5 ma v ds =0.5v, v dd =4.8v 9.0 voltage detector 2 only 0.5 1.0 2.0 m v sen =4.8v 0.4 1.6 a 100 ppm/?c
13 input pins [rv5ve001b] topt=25?c (note) unless otherwise provided, v dd = 4.8v. rv5ve0 symbol item i leak input leakage current v il control switch low level input voltage v ih control switch high level input voltage v sil schmitt trigger low level input voltage v sih schmitt trigger high level input voltage v hys schmitt trigger hysteresis voltage conditions min. typ. max. unit C1 1 a csw1 to 4 0 0.8 v csw1 to 4 2.0 v dd v optional v optional v optional v
14 ? rv5ve001c (note 1) unless otherwise provided, v dd = 3.6v, i out = 50ma, co = 10f, rbe = 100k . (note 2) use external transistor with h fe 3 100. (note 3) quiescent current = operating current of regulators 1, 2 + 0.6/rbe. (note 4) supply current = quiescent (no load) current + load current/h fe . voltage regulator 3 [rv5ve001c] voltage regulators 1, 2 [rv5ve001c] (note) unless otherwise provided, v dd = 3.6v, i out = 30ma topt=25?c topt=25?c rv5ve0 symbol item r out 1 , 2 output voltage i ss 1 , 2 quiescent current iopr 1 , 2 supply current v dif 1 , 2 dropout voltage ? v out load regulation ? i out ? v out line regulation ? v in rr ripple rejection i lim1,2 current limit ? v out output voltage ? topt temperature coefficient conditions min. typ. max. unit 2.925 3.000 3.075 v i out =0ma 100 a i out =80ma 1 ma r out 1 , 2 =3.0v,i out =80ma 0.05 0.3 v r out 1 , 2 =3.0v 1ma i out 80ma 50 mv r out 1 , 2 +0.3v v in 10.0v 0.05 0.3 % /v f=120h z ,ripple 0.5vrms 40 60 db base current of i b 1 , 2 of 310ma pnp t ransistor 100 ppm/?c symbol item r out 3 output voltage i ss 3 supply current v dif 3 dropout voltage ? v out load regulation ? i out ? v out line regulation ? v in i lim3 current limit ? v out output voltage ? topt temperature coefficient conditions min. typ. max. unit 2.925 3.000 3.075 v 5.0 10.0 a r out 3 =3.0v,i out =35ma 0.3 v r out 3 =3.0v 1ma i out 35ma 50 mv r out 3 +0.5v v in 10.0v 0.05 0.3 % /v 100 300 ma 100 ppm/?c
15 voltage regulator 4 [rv5ve001c] topt=25?c (note) unless otherwise provided, v dd = 3.6v, i out = 10ma voltage detectors 1,2 [rv5ve001c] topt=25?c (note) unless otherwise provided, v dd = 6.0v. rv5ve0 symbol item r out 4 output voltage i ss 4 supply current v dif 4 dropout voltage ? v out load regulation ? i out ? v out line regulation ? v in i lim4 current limit ? v out output voltage ? topt temperature coefficient conditions min. typ. max. unit 2.925 3.000 3.075 v 1.1 3.3 a r out 4 =3.0v,i out =15ma 0.3 v r out 4 =3.0v 1ma i out 15ma 50 mv r out 4 +0.5v v in 10.0v 0.05 0.3 % /v 100 300 ma 100 ppm/?c symbol item Cv det 1 detector threshold 1 Cv det 2 detector threshold 2 v hys detector threshold hysteresis i ss 5 i ss 6 supply current i out output current r d output delay resistor i sen sense pin input current ? v det detector threshold ? topt temperature coefficient conditions min. typ. max. unit voltage detector 1 3.315 3.400 3.485 v voltage detector 2 2.438 2.500 2.562 v (Cv det ) 0.05 v voltage detector 1,v dd =3.6v 1.1 3.3 a voltage detector 2,v dd =3.6v 1.3 3.9 a v ds =0.5v, v dd =1.5v 1.5 ma v ds =0.5v, v dd =3.6v 6.5 voltage detector 2 only 0.5 1.0 2.0 m v sen =3.6v 0.3 1.2 a 100 ppm/?c
16 input pins [rv5ve001c] topt=25?c (note) unless otherwise provided, v dd = 3.6v. rv5ve0 symbol item i leak input leakage current v il control switch low level input voltage v ih control switch high level input voltage v sil schmitt trigger low level input voltage v sih schmitt trigger high level input voltage v hys schmitt trigger hysteresis voltage conditions min. typ. max. unit C1 1 a csw1 to 4 0 0.6 v csw1 to 4 1.6 v dd v optional v optional v optional v
17 ? regulators 1,2 operation r out4 i bc1,2 v dd r2 r1 gnd csw1,2 level shift r out1,2 current limit circuit vref + c 1,2 each of regulators 1 and 2 is operating with an external pnp transistor as shown in the above figure. regulators 1 and 2 divide output voltage v out by feed-back registers r1 and r2, and the divided voltage at the node between registers r1 and r2 is compared with the reference voltage by error amplifier, so that the base cur- rent of the pnp transistor is adjusted, and a constant voltage is output. the output current from each of regulators 1 and 2 is monitored by current limitter, and when the output current exceeds a limit current, current limitter limits the base current of the pnp transistor to the specified limit current. the level of input signals to csw 1, 2 is set at the same level as the output voltage level of r out 4 by built-in level shift circuit. phase compensation is made externally with c 1,2 . ? regulators 3,4 vref csw3 r out4 v dd r2 r1 gnd a r out3,4 current limit circuit level shift + regulators 3 and 4 divide output voltage v out by feed-back registers r1 and r2, and the divided voltage at the node between registers r1 and r2 is compared with the reference voltage by error amplifier, so that a con- stant voltage is output. the output current from each of regulators 3 and 4 is monitored by current limitter, and when the output current exceeds a limit current, current limitter limits the output current to the limit current. regulator 4 is connected at point to the gnd in the above figure, so that regulator 4 is always in operation. the level of input signals to csw1, 2 is set at the same level as the output voltage level of r out 4 by built-in lev- el shift circuits. rv5ve0
18 ? detector 1 v dd current source ra rb rc tr.1 output tr. v sen1 d out gnd nch vref + operation diagram a b released voltage +v det detected voltage ? det minimum operating voltage gnd step gnd output voltage 1 2 3 4 5 detector threshold hysteresis step step 1 step 2 step 3 step 4 step 5 comparator(+)pin input voltage iii ii iii comparator output hl l lh tr. 1 off on on on off output tr. nch off on indefinite on off i . rb + rc ra + rb + rc v dd ii . rb ra + rb v dd step 1. output voltage is equal to pull-up voltage. step 2. when input voltage (v sen 1 )reaches the state of vref 3 v sen 1 (rb+rc)/(ra+rb+rc)at point a (detected voltage Cv det ), the output of comparator is reversed, so that output voltage becomes gnd. step 3. output voltage becomes indefinite when power source voltage (v dd ) is smaller than minimum operating voltage. when the output is pulled- up,v dd is output. step 4. output voltage becomes equal to gnd. step 5. when input voltage to (v sen 1 ) reaches the state of vref v sen 1 rb/(ra + rb) at point b (released voltage +v det ), the output of comparator is reversed, so that output voltage becomes equal to pulled-up voltage. step of operation the following descriptions deal with v dd pin and v sen 1 pin as connected each other, but detector 1 can be detect- ed the different voltage from v dd through v sen 1 pin. rv5ve0
19 ? detector 2 c d current source vref ra rb rc tr.1 tr.2 rb output capacitor gnd v dd reset v sen2 + operation diagram a b minimum operating voltage gnd gnd output voltage step 1 2 3 4 5 delay time detector threshold hysteresis released voltage +v det detected voltage ? det i . rb + rc ra + rb + rc v dd ii . rb ra + rb v dd step 1. output voltage is equal to pull-up voltage. step 2. when input voltage (v sen 2 ) reaches the state of vref 3 v sen 2 (rb+rc)/(ra+rb+rc)at point a (detected voltage C v det ), the output of compara- tor is reversed, so that output voltage becomes gnd. discharging is performed from c d pin connected to external capacitor. no delay time is generated. step 3. output voltage becomes indefinite when power source voltage (v dd ) is smaller than minimum operating voltage. when the output is pulled- up,v dd is output. step 4. output voltage becomes equal to gnd. step 5. when input voltage (v sen 2 ) reaches the state of vref v sen 2 rb/(ra + rb) at point b (released voltage +v det ), the output of comparator is reversed, and the external capacitor is charged through c d pin,so that output voltage becomes equal to pulled-up voltage after a delay timet d (= 0.69 10 6 c d ). step of operation the following descriptions deal with v dd pin and v sen 2 pin as connected each other, but detector 2 can be detect- ed the different voltage from v dd through v sen 2 pin. rv5ve0 step step 1 step 2 step 3 step 4 step 5 comparato (+) pin input voltage iii ii iii comparator output hl l lh tr. 1 off on on on off output tr. nch off on indefinite on off
20 ? test circuit 1 100k w 100k w 1 16 tr. 100k w c d h/l 0.1 f 10 f 10 f 0.1 f 10 f v dd tr. 8 9 100k w h/l h/l tr : 2sb804 (h fe =150) i ss csw1 csw2 csw3 regulator 1 h l l regulator 2 l h l regulator 3 l l h regulator 4 l l l detector 1 l l l detector 2 l l l test circuits (rv5ve001a,b,c) output voltage current limit (regulator 3, 4) quiescent current output voltage temperature coefficient dropout voltage detector threshold load regulation detector threshold hysteresis line regulation output voltage transient response ? test circuit 2 8 9 1 16 h/l h/l open 10 f 100k w tr. 10 f 100k w tr open open v dd tr : 2sb804 (h fe =150) csw1 csw2 regulator 1 h l regulator 2 l h ripple rejection (regulator 1, 2) rv5ve0
21 ? test circuit 3 open open open h/l h/l i lim1 1 16 8 9 i lim2 v dd a a csw1 csw2 regulator 1 h l regulator 2 l h current limit (regulator 1, 2) ? test circuit 4 open open open 0.5v v dd 1 16 8 9 0.5v i out2 i out1 a a output current (detector 1, 2) rv5ve0
22 typical characteristics (rv5ve001a) 1) output voltage vs. input voltage regulator 1,2 (5v) 1 output voltage v out (v) 2 3 4 5 6 024681012 input voltage v in (v) i out =50ma ?0?c 25?c 80?c input voltage v in (v) 1 output voltage v out (v) 2 3 4 5 6 024681012 i out =30ma ?0?c 25?c 80?c 1 output voltage v out (v) 2 3 4 5 6 024681012 input voltage v in (v) i out =10ma ?0?c 25?c 80?c i out =50ma output voltage v out (v) 4.8 4.9 5.0 5.1 4.8 5.0 5.2 5.4 5.5 25?c 80?c input voltage v in (v) ?0?c i out =10ma output voltage v out (v) 4.8 4.9 5.0 5.1 4.8 5.0 5.2 5.4 5.6 input voltage v in (v) ?0?c 80?c 25?c ? regulator section regulator 3 (5v) (zoomed) regulator 1,2 (5v) i out =30ma output voltage v out (v) 4.8 4.9 5.0 5.1 4.8 5.0 5.2 5.4 5.6 input voltage v in (v) ?0?c 80?c 25?c (zoomed) regulator 3 (5v) (zoomed) regulator 4 (5v) regulator 4 (5v) rv5ve0
23 2) output voltage vs. output current 3) dropout voltage vs. output curret output voltage v out (v) v dd =6.0v 4.8 4.9 5.0 5.1 0 100 200 300 output current i out (ma) 80?c 25?c ?0?c output voltage v out (v) 4.0 output current i out (ma) 0 4.2 4.6 4.4 4.8 5.0 5.2 50 100 150 200 v dd =6.0v ?0?c 25?c 80?c output current i out (ma) 0 100 200 300 dropout voltage v dif (v) 0.0 0.1 0.2 0.3 25?c 80?c ?0?c v dd =6.0v output voltage v out (v) output current i out (ma) 0 100 200 300 4.0 4.2 4.4 4.6 4.8 5.0 5.2 ?0?c 80?c 25?c output current i out (ma) 0 100 200 300 dropout voltage v dif (v) 0.0 0.5 1.0 1.5 2.0 ?0?c 80?c 25?c regulator 1,2 (5v) regulator 3 (5v) regulator 4 (5v) regulator 1,2 (5v) regulator 3 (5v) rv5ve0
24 4) output voltage vs.temperature dropout voltage v dif (v) output current i out (ma) 0 0.0 50 100 100 100 0.5 1.0 1.5 2.0 80?c 25?c ?0?c temperature topt(?c) output voltage v out (v) ?0 4.96 ?0 0 20 60 80 4.98 5.00 5.02 5.04 (5v) 40 regulator 2 v dd =6.0v regulator 1: i out =50ma regulator 2: i out =50ma regulator 3: i out =30ma regulator 4: i out =10ma regulator 3 100 regulator 1 regulator 4 i out =1ma c out =4.7? 0 012 0 1 2 3 4 5 6 7 8 345 time t(ms) input voltage/output voltage v in /v out (v) input voltage output voltage v dd = 6.0v 0.5vrms regulator 1,2: i out =50ma c = 4.7 ? regulator 3 : i out =30ma c = 0.1? regulator 4 : i out =10ma c = 0.1? 10 100 1000 10000 0 10 20 30 40 50 60 70 frequency f(hz) ripple rejection(db) regulator 1,2 regulator 4 regulator 3 regulator 4 (5v) 5) ripple rejection vs. frequency 6) line transient response 1 regulator 1,2 (5v) i out =1ma c out =0.1 f 0 12345 time t(ms) 0 1 2 3 4 5 6 7 8 input voltage/output voltage v in /v out (v) input voltage output voltage regulator 3 (5v) rv5ve0
25 7) line transient response 2 i out =1ma c out =0.1 f input voltage/output voltage v in /v out (v) 0 1 2 3 4 5 6 7 8 0 012345 time t(ms) input voltage output voltage 0 012345 time t(ms) i out =10ma c out =4.7f input voltage/output voltage v in /v out (v) 0 1 2 3 4 5 6 7 8 input voltage output voltage i out =10ma c out =0.1 f 0 012345 time t(ms) input voltage/output voltage v in /v out (v) 0 1 2 3 4 5 6 7 8 input voltage output voltage 0 012345 time t(ms) i out =10ma c out =0.1 f input voltage/output voltage v in /v out (v) 0 1 2 3 4 5 6 7 8 input voltage output voltage regulator 4 (5v) regulator 4 (5v) regulator 1,2 (5v) regulator 3 (5v) rv5ve0
26 8) supply current vs. input voltage 9) supply current vs. temperature input voltage v dd (v) 0 2 46 810 12 supply current i ss (?) 0 2 4 6 8 10 input voltage v dd (v) 0 2 46 810 12 supply current i ss (?) 0 1 2 3 4 5 supply current i ss (?) 0 2 4 6 8 10 temperature topt(?c) 100 60 40 20 80 0 ?0 ?0 v dd =6.0v input voltage v dd (v) 0 2 46 810 12 supply current i ss (?) 0 2 4 6 8 10 supply current i ss ( ?) 0 2 4 6 8 10 v dd =6.0v temperature topt(?c) 100 60 40 20 80 0 ?0 ?0 regulator 1,2 (5v) regulator 3 (5v) regulator 4 (5v) regulator 1,2 (5v) regulator 3 (5v) rv5ve0
27 10) output voltage transient response for csw input voltage step v dd =6.0v temperature topt(?c) 100 60 40 20 80 ?0 ?0 0 supply current i ss (?) 0 1 2 3 4 5 v dd =6.0v i out =50ma c out =10 ? 0 output voltage v out (v) 1 2 7 6 5 4 3 time t(?) 0 100 200 300 v dd =6.0v i out =10ma c out =0.1 f 0 output voltage v out (v) 1 2 7 6 5 4 3 time t(?) 0 400 800 1200 v dd =6.0v i out =30ma c out =0.1 f 0 output voltage v out (v) 1 2 7 6 5 4 3 time t(?) 0 200 400 600 regulator 4 (5v) regulator 4 (5v) regulator 1,2 (5v) regulator 3 (5v) rv5ve0 (note) 0s point is synchronous with being h state of control switch.
28 1) output voltage vs. input voltage detector 1,2 80?c 25?c 0.0 0.5 1.0 1.5 2.0 2.5 3.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 4.0 3.5 input voltage v dd (v) output voltage v out (v) ? det1,2 =2.0v ?0?c 25?c input voltage v dd (v) 0 246 810 12 0 2 4 1 3 supply current i ss (?) 80?c ?0?c 5.7 5.6 5.5 5.4 5.3 temperature topt(?c) 100 60 40 20 80 0 ?0 ?0 detected/released voltage v det (v) ? det1 +v det1 80?c 25?c ?0?c v ds =0.5v 0 0 4 8 12 16 20 24 1 2 3 456 7 output current i out (v) input voltage v dd (v) 4.8 4.7 4.6 4.5 4.4 temperature topt(?c) 100 60 40 20 80 0 ?0 ?0 detected/released voltage v det (v) ? det2 +v det2 ? detectors detector 1 detector 1,2 0 4 10 2 6 supply current i ss (?) input voltage v dd (v) 0 246 810 12 8 80?c 25?c ?0?c detector 2 3) supply current vs. input voltage 2) output current vs. input voltage 4) detected/released voltage vs. temperature detector 1 detector 2 rv5ve0
29 5) output delay time (falling edge) vs. load capacitance detector 1,2 topt = 25?c detector 2 load capacitance c out (f) output delay time t phl (s) 10 -3 10 -7 10 -9 10 -8 10 -6 10 -4 10 -5 10 -6 detector 2 detector 1 without c d v dd = 3.0v topt = 25?c without c out c d pin external capacitance c d (f) output delay time t phl (s) 10 -5 10 -6 10 -9 10 -8 10 -7 10 -6 topt = 25?c without c out and c d input voltage v dd (v) output delay time t plh (s) 02 4 10 8 6 10 -3 10 -4 10 -5 detector 2 detector 1 detector 1 detector 1,2 topt = 25?c output delay time t plh (s) c d pin external capacitance c d (f) 10 -0 10 -1 10 -2 10 -3 10 -9 10 -8 10 -7 10 -6 detector 2 7) output delay time (falling edge) vs. c d pin external capacitance 6) output delay time (rising edge) vs. input voltage 8) output delay time (rising edge) vs. c d pin external capacitance rv5ve0
30 typical characteristics (rv5ve001b) 1) output voltage vs. input voltage regulator 1,2 (4v) 1 output voltage v out (v) 2 3 4 5 0 2 4 6 8 10 12 input voltage v in (v) i out =50ma ?0?c 80?c 25?c i out =30ma 0 2 4 6 8 10 12 input voltage v in (v) 1 output voltage v out (v) 2 3 4 5 ?0?c 80?c 25?c i out =10ma 1 output voltage v out (v) 2 3 4 5 0 2 4 6 8 10 12 input voltage v in (v) ?0?c 25?c 80?c 3.8 4.0 4.2 4.4 4.6 input voltage v in (v) 3.8 4.0 3.9 4.1 output voltage v out (v) i out =50ma ?0?c 25?c 80?c i out =10ma 3.8 4.0 3.9 4.1 output voltage v out (v) 3.8 4.0 4.2 4.4 4.6 input voltage v in (v) 4 ?0?c 25?c 80?c ? regulators regulator 3 (4v) (zoomed) regulator 1,2 (4v) i out =30ma 3.8 4.0 3.9 4.1 output voltage v out (v) 3.8 4.0 4.2 4.4 4.6 input voltage v in (v) ?0?c 80?c 25?c (zoomed) regulator 3 (4v) (zoomed) regulator 4 (4v) regulator 4 (4v) rv5ve0
31 2) output voltage vs. output current 3) dropout voltage vs. output curret v dd =4.8v output voltage v out (v) 3.8 3.9 4.0 4.1 0 100 200 300 output current i out (ma) ?0?c 25?c 80?c v dd =4.8v output voltage v out (v) output current i out (ma) 0 50 100 150 3.0 3.2 3.4 3.6 3.8 4.0 4.2 ?0?c 25?c 80?c output current i out (ma) 0 100 200 300 dropout voltage v dif (v) 0.0 0.1 0.2 0.3 80?c 25?c ?0?c v dd =4.8v output voltage v out (v) output current i out (ma) 0 100 200 300 3.0 3.2 3.4 3.6 3.8 4.0 4.2 ?0?c 25?c 80?c output current i out (ma) 0 100 200 300 dropout voltage v dif (v) 0.0 0.2 0.8 1.4 2.0 1.8 1.6 1.2 1.0 0.6 0.4 80?c 25?c ?0?c regulator 1,2 (4v) regulator 3 (4v) regulator 4 (4v) regulator 1,2 (4v) regulator 3 (4v) rv5ve0
32 4) output voltage vs.temperature output current i out (ma) 0 20 40 60 100 dropout voltage v dif (v) 0.0 0.5 1.0 1.5 2.0 80 25?c 80?c ?0?c (4v) output voltage v out (v) 3.96 3.98 4.00 4.02 4.04 ?0 temperature topt(?c) ?0 0 20 60 80 40 100 v dd =4.8v regulator 1: i out =50ma regulator 2: i out =50ma regulator 3: i out =30ma regulator 4: i out =10ma regulator 2 regulator 1 regulator 3 regulator 4 0 012345 time t(ms) 0 1 2 3 4 5 6 7 8 input voltage/output voltage v in /v out (v) i out =1ma c out =4.7 f input voltage output voltage v dd = 4.8v 0.5vrms regulator 1,2: i out =50ma c = 4.7? regulator 3 : i out =30ma c = 0.1 ? regulator 4 : i out =10ma c = 0.1 ? 10 100 1000 10000 frequency f(hz) 0 10 20 30 40 50 60 70 ripple rejection(db) regulator 3 regulator 4 regulator 1,2 regulator 4 (4v) 5) ripple rejection vs. frequency 6) line transient response 1 regulator 1,2 (4v) i out =1ma c out =0.1 f 0 012345 time t(ms) 0 1 2 3 4 5 6 7 8 input voltage/output voltage v in /v out (v) input voltage output voltage regulator 3 (4v) rv5ve0
33 7) line transient response 2 i out =1ma c out =0.1 f 0 012345 time t(ms) input voltage/output voltage v in /v out (v) 0 1 2 3 4 5 6 7 8 input voltage output voltage 0 012345 time t(ms) input voltage/output voltage v in /v out (v) 0 1 2 3 4 5 6 7 8 i out =10ma c out =4.7 f input voltage output voltage 0 0 1 23 4 5 time t(ms) input voltage/output voltage v in /v out (v) 0 1 2 3 4 5 6 7 8 i out =10ma c out =0.1 f input voltage output voltage 0 012345 time t(ms) input voltage/output voltage v in /v out (v) 0 1 2 3 4 5 6 7 8 i out =10ma c out =0.1 f input voltage output voltage regulator 4 (4v) regulator 4 (4v) regulator 1,2 (4v) regulator 3 (4v) rv5ve0
34 8) supply current vs. input voltage 9) supply current vs. temperature supply current i ss ( ?) 0 2 4 6 8 10 input voltage v dd (v) 0 2 4 6 810 12 input voltage v dd (v) 0 2 4 6 810 12 supply current i ss (a) 0 1 2 3 4 5 v dd =4.8v temperature topt(?c) 100 60 40 20 80 0 ?0 ?0 supply current i ss (?) 0 2 4 6 8 10 input voltage v dd (v) 0 2 4 6 810 12 supply current i ss (?) 0 2 4 6 8 10 v dd =4.8v temperature topt(?c) 100 60 40 20 80 0 ?0 ?0 supply current i ss (?) 0 2 4 6 8 10 regulator 1,2 (4v) regulator 3 (4v) regulator 4 (4v) regulator 1,2 (4v) regulator 3 (4v) rv5ve0
35 10) output voltage transient response for csw input voltage step v dd =4.8v temperature topt(?c) 100 60 40 20 80 0 ?0 ?0 supply current i ss (?) 0 1 2 3 4 5 v dd =4.8v i out =50ma c out =10 ? 0 output voltage v out (v) 1 2 7 6 5 4 3 time t(?) 0 100 200 300 v dd =4.8v i out =10ma c out =0.1 f time t(?) 0 400 800 1200 0 output voltage v out (v) 1 2 7 6 5 4 3 v dd =4.8v i out =30ma c out =0.1 f time t(?) 0 200 400 600 0 output voltage v out [v] 1 2 7 6 5 4 3 regulator 4 (4v) regulator 4 (4v) regulator 1,2 (4v) regulator 3 (4v) rv5ve0 (note) 0s point is synchronous with being h state of control switch.
36 1) output voltage vs. input voltage detector 1,2 ? det1,2 =2.0v 80?c 25?c ?0?c 0.0 4.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 output voltage v out (v) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 input voltage v dd (v) 80?c 25?c ?0?c 0 2 4 1 3 supply current i ss (?) input voltage v dd (v) 0 246 8 10 12 temperature topt(?c) 100 60 40 20 80 0 ?0 ?0 4.7 4.6 4.5 4.4 4.3 detected/released voltage v det (v) ? det1 +v det1 vds=0.5v ?0?c 0 12 3 4 5 6 7 input voltage v dd (v) 0 4 8 12 16 20 24 output voltage v out (v) 25?c 80?c temperature topt(?c) 100 60 40 20 80 0 ?0 ?0 3.8 3.7 3.6 3.5 3.4 detected/released voltage v det (v) ? det2 +v det2 ? detectors detector 1 detector 1,2 80?c 25?c ?0?c 0 4 10 2 6 supply current i ss (?) 8 input voltage v dd (v) 0 246 8 10 12 detector 2 3) supply current vs. input voltage 2) output current vs. input voltage 4) detected/released voltage vs. temperature detector 1 detector 2 rv5ve0
37 detector 1,2 topt = 25?c detector 2 output delay time t phl (s) 10 -3 load capacitance c out (f) detector 1 detector 2 10 -6 10 -7 10 -9 10 -8 10 -5 10 -6 10 -4 without c d v dd = 3.0v topt = 25?c without c out output delay time t phl (s) 10 -9 10 -8 10 -7 10 -6 10 -5 10 -6 c d pin external capacitance c d (f) topt = 25?c without c out and c d input voltage v dd (v) 02 4 10 8 6 detector 2 detector 1 10 -3 10 -4 10 -5 output delay time t plh (s) detector 2 detector 1,2 topt = 25?c output delay time t plh (s) 10 -1 10 -0 10 -2 10 -3 10 -9 10 -8 10 -6 10 -7 c d pin external capacitance c d (f) detector 2 rv5ve0 5) output delay time (falling edge) vs. load capacitance 7) output delay time (falling edge) vs. c d pin external capacitance 6) output delay time (rising edge) vs. input voltage 8) output delay time (rising edge) vs. c d pin external capacitance
38 typical characteristics (rv5ve001c) 1) output voltage vs. input voltage regulator 1,2 (3v) 024681012 input voltage v in (v) i out =50ma 2.2 output voltage v out (v) 2.4 2.6 2.8 3.0 2.0 1.8 3.2 80?c 25?c ?0?c 1.5 output voltage v out (v) 2.0 2.5 3.0 3.5 024681012 input voltage v in (v) i out =30ma ?0?c 80?c 25?c output voltage v out (v) 1.5 2.0 2.5 3.0 i out =10ma ?0?c 25?c 80?c 024681012 input voltage v in (v) 80?c i out =50ma 2.8 3.0 3.2 3.4 3.6 input voltage v in (v) 2.6 2.8 3.0 2.9 3.1 output voltage v out (v) ?0?c 25?c ?0?c 25?c 80?c i out =10ma 2.8 3.0 2.9 3.1 output voltage v out (v) 2.8 3.0 3.2 3.4 3.6 input voltage v in (v) ? regulator section regulator 3 (3v) (zoomed) regulator 1,2 (3v) ?0?c 25?c 80?c 2.8 3.0 3.2 3.4 3.6 input voltage v in (v) 2.8 3.0 2.9 3.1 output voltage v out (v) i out =30ma (zoomed) regulator 3 (3v) (zoomed) regulator 4 (3v) regulator 4 (3v) rv5ve0
39 2) output voltage vs. output current 3) dropout voltage vs. output current v dd =3.6v output voltage v out (v) 2.8 2.9 3.0 3.1 0 100 200 300 output current i out( ma) 80?c ?0?c 25?c output current i out (ma) 0 50 100 150 v dd =3.6v 25?c output voltage v out (v) 2.0 2.2 2.4 2.6 2.8 3.0 3.2 80?c ?0?c 25?c 80?c ?0?c 0 100 200 300 output current i out (ma) dropout voltage v out (v) 0.0 0.1 0.2 0.3 output voltage v out (v) 2.0 2.2 2.6 2.4 2.8 3.0 v dd =3.6v ?0?c 25?c 80?c 0 100 200 300 output current i out (ma) output current i out (ma) 0 100 200 300 dropout voltage v dif (v) 0.0 0.5 1.0 1.5 2.0 80?c ?0?c 25?c regulator 1,2 (3v) regulator 3 (3v) regulator 4 (3v) regulator 1,2 (3v) regulator 3 (3v) rv5ve0
40 4) output voltage vs.temperature dropout voltage v dif (v) 0.0 0.5 1.0 1.5 2.0 80?c 25?c ?0?c output current i out (ma) 0 20 40 60 100 80 temperature topt(?c) ?0 ?0 0 20 40 60 80 100 2.96 output voltage v out (v) 2.97 2.98 2.99 3.00 3.01 3.02 v dd =3.6v regulator 1: i out =50ma regulator 2: i out =50ma regulator 3: i out =30ma regulator 4: i out =10ma regulator 3 regulator 1 regulator 4 regulator 2 0 1 23 4 5 time t(ms) 0 1 2 3 4 5 6 7 8 input voltage/output voltage v in /v out (v) i out =1ma c out =4.7 f input voltage output voltage 10 100 1000 10000 frequency f(hz) 0 10 20 30 40 50 60 70 ripple rejection(db) regulator 1,2 regulator 3 regulator 4 v dd = 3.6v 0.5vrms regulator 1,2: i out =50ma c = 4.7 ? regulator 3 : i out =30ma c = 0.1 ? regulator 4 : i out =10ma c = 0.1 ? regulator 4 (3v) 5) ripple rejection vs. frequency 6) line transient response 1 regulator 1,2 (3v) i out =1ma c out =0.1 f 0 1 23 4 5 time t(ms) 0 1 2 3 4 5 6 7 8 input voltage/output voltage v in /v out (v) input voltage output voltage regulator 3 (3v) rv5ve0
41 7) line transient response 2 i out =1ma c out =0.1 f input voltage/output voltage v in /v out (v) 0 1 2 3 4 5 6 7 8 0 012345 time t(ms) input voltage output voltage i out =10ma c out =4.7 f input voltage/output voltage v in/ v out (v) 0 1 2 3 4 5 6 7 8 0 012345 time t(ms) input voltage output voltage i out =10ma c out =0.1 f 0 012345 time t(ms) input voltage/output voltage v in /v out (v) 0 1 2 3 4 5 6 7 8 input voltage output voltage i out =10ma c out =0.1 f 0 012345 time t(ms) input voltage/output voltage v in /v out (v) 0 1 2 3 4 5 6 7 8 input voltage output voltage regulator 4 (3v) regulator 4 (3v) regulator 1,2 (3v) regulator 3 (3v) rv5ve0
42 8) supply current vs. input voltage 9) supply current vs. temperature supply current i ss (?) 0 2 4 6 8 10 input voltage v dd (v) 0 2 46 810 12 supply current i ss (?) 0 1 2 3 4 5 input voltage v dd (v) 0 2 46 810 12 v dd =3.6v temperature topt(?c) 100 60 40 20 80 0 ?0 ?0 supply current i ss (?) 0 2 4 6 8 10 supply current i ss ( ?) 0 2 4 6 8 10 input voltage v dd (v) 0 2 46 810 12 v dd =3.6v temperature topt(?c) 100 60 40 20 80 0 ?0 ?0 supply current i ss ( ?) 0 2 4 6 8 10 regulator 1,2 (3v) regulator 3 (3v) regulator 4 (3v) regulator 1,2 (3v) regulator 3 (3v) rv5ve0
43 10) output voltage transient response for csw input voltage step supply current i ss ( ?) 0 1 2 3 4 5 temperature topt(?c) 100 60 40 20 80 ?0 ?0 0 v dd =3.6v v dd =3.6v i out =50ma c out =10 ? time t(?) 0 100 200 300 0 output voltage v out (v) 1 2 7 6 5 4 3 v dd =3.6v i out =10ma c out =0.1 f time t(?) 0 400 800 1200 0 output voltage v out (v) 1 2 7 6 5 4 3 time t(?) 0 200 400 600 0 output voltage v out (v) 1 2 7 6 5 4 3 v dd =3.6v i out =30ma c out =0.1 f regulator 4 (3v) regulator 4 (3v) regulator 1,2 (3v) regulator 3 (3v) rv5ve0 (note) control switch becomes on ( h ) at 0s.
44 1) output voltage vs. input voltage detector 1,2 ? det1,2 =2.0v 80?c 25?c ?0?c 0.0 0.5 1.0 1.5 2.0 2.5 3.0 4.0 3.5 output voltage v out (v) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 input voltage v dd (v) 0 2 4 1 3 supply current i ss ( ?) input voltage v dd (v) 0 246 810 12 25?c 80?c ?0?c 3.7 3.6 3.5 3.4 3.3 detected/released voltage v det (v) temperature topt(?c) 100 60 40 20 80 0 ?0 ?0 +v det1 ? det1 0 1 2 3 456 7 input voltage v dd (v) 25?c 80?c ?0?c vsd=0.5v 0 4 8 12 16 20 24 output current i out (ma) 2.8 2.7 2.6 2.5 2.4 detected/released voltage v det (v) temperature topt(?c) 100 60 40 20 80 0 ?0 ?0 +v det2 ? det2 ? detectors detector 1 detector 1,2 0 4 10 2 6 supply current i ss (?) 8 input voltage v dd (v) 0 246 810 12 80?c 25?c ?0?c detector 2 3) supply current vs. input voltage 2) output current vs. input voltage 4) detected/released voltage vs. temperature detector 1 detector 2 rv5ve0
45 detector 1,2 10 -6 detector 1 detector 2 load capacitance c out (f) output delay time t phl (s) 10 -3 10 -5 10 -6 10 -7 10 -9 10 -8 10 -4 topt = 25?c detector 2 without c d v dd = 3.0v topt = 25?c without c d c d pin external capacitance c d (f) output delay time t phl (s) 10 -9 10 -8 10 -5 10 -6 10 -6 10 -7 topt = 25?c without c out and c d input voltage v dd (v) output delay time t plh (s) 02 4 10 8 6 10 -3 10 -4 10 -5 detector 2 detector 1 detector 2 detector 1,2 output delay time t plh (s) 10 -1 10 -0 10 -2 10 -3 c d pin external capacitance c d (f) 10 -9 10 -8 10 -6 10 -7 topt = 25?c detector 2 rv5ve0 5) output delay time (falling edge) vs. load capacitance 7) output delay time (falling edge) vs. c d pin external capacitance 6) output delay time (rising edge) vs. input voltage 8) output delay time (rising edge) vs. c d pin external capacitance
46 typical application ? rv5ve001 rv5ve0 in this example of the circuit, the output of regulator 4 is used as the power source for cpu. the voltage input to csw 1, 2, 3 pins is subject to level shift within the ic so as to have the same level as that of the voltage of cpu. therefore csw 1, 2, 3 pins can be directly connected to cpu. detector 1 monitors the voltage of the battery and detector 2 monitors the voltage of the power source for cpu. application for cellular phones (rv5ve001 ) vcc c5 c1 c2 c4 c3 c d tr r1 r2 r3 r4 tr v dd r out4 v sen2 c d reset d out r out1 i bc1 gnd r out3 v sen1 csw3 csw1 r out2 i bc2 i/o logic unit cpu int reset memory unit transmitter unit receiver/audio unit sbd csw2 i/o i/o r 5ve001 c1,2,5=10f / c3,4=0.1f / c d =0.1f r1,2,3,4=100k tr: 2sb799(nec pnp type,h fe =100 to 200) sbd: ma717(panasonic) application hints when using these ics, be sure to take care of the following points : ? minimize the impedance of v dd and gnd wiring. in particular, with respect to the v dd wiring, the output cur- rent of regulators flows thereinto, so that when the wiring impedance is high, the operation of the ic tends to be unstable and is vulnerable to noise. ? provide a capacitor with a capacitance of about 10f between v dd pin and gnd pin with a minimum wiring length. ? rush current flows into the capacitor connected to the output of regulators at the start of the operation of the regulators. in particular, regulators 1, 2 are equipped with external pnp transistor and accordingly have excellent drive performance. therefore, when regulators 1, 2 start to operate, for example, under the conditions that h fe of external pnp transistor is 100 and the base current of the limiter is 5ma, a rush current of 500ma flows into the regulators. when the wiring impedance is high, the power source voltage applied to ic tends to be varied by the rush current, so that the operation of ic may be adversely affected by the variation of the power source voltage. ? in these ics phase compensation is made for securing stable operation even when the load current is varied. select the capacitors c1 to c4 conecting the pin r out 1 to r out 4 with good frequency characteristics and small esr. ? be sure to connect a resistor with a resistance of about 100k between the base and the emitter for preventing the oscillation. ? set external parts as close as possible to the ic and minimize the connection between the parts and the ic. ? when using a capacitor connected to c d pin, use a schottky barrier diode (sbd) to discharge c d capacitor at the time of abrupt fluctuation of power source voltage.
47 application for cellular phones (rv5ve0 :optional mask version) this optional mask version's application operates as follows. regulator 1, 2 : regulator 1 and 2 can be enabled and disabled through toggle input and cpu signal csw1. regulator 3 : regulator 3 can be enabled and disabled through toggle input and cpu signal csw2. regulator 4 : regulator 4 is always enabled by dry cells (when the v dd voltage is maintained higher than minimum operating voltage). the output of regulator 4 is not only the power source for cpu but also the level shift voltage of csw 1, 2 pins. therefor csw1, 2 pins can be direct- ly connected to cpu. detector 1, 2 : detector 1 and 2 monitor the v dd level and the output of regulator 4 respectively. furthermore detector 2 can generate the output-delay time (time delay to output rising edge) by connecting a capacitor to c d pin. tff : tff can be reset by the output of power-on-reset and detector 2 (through one shot pulse generator), while tff is in the reset state regulator 1, regulator 2 and regulator 3 are dis- abled. one shot pulse generator operation input 100 s output rv5ve0
48 application for cellular phones (rv5ve0 ) 2 level shift i bc1 v dd mechanical switch r5 q c6 csw1 sbd c d gnd r t i shot pulse generator r egulator 2 r egulator 3 r egulator 4 detector 2 detector 1 toggle input r out1 i bc2 r out4 v sen1 d out v sen2 reset r6 r1 c1 c2 c3 r2 tr tr r4 r3 memory/logic unit transmitter unit receiver/audio unit cpu reset vcc i/o i/o int 1 3 10 9 8 7 6 4 5 11 12 13 14 15 16 csw2 c d r out3 r out2 c4 c5 level shift r egulator 2 c1,2,5=10f/c3,4=0.1f/c6=1f/c d =0.1f r1,2,3,4=100k /r5=10k /r6=47 tr: 2sb799(nec pnp type,h fe =100 to 200) sbd: ma717(panasonic) rv5ve0

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